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m-888 0 dtm f t ransceiver advance d cmo s technolog y fo r lo w powe r consump - tio n an d increase d nois e immunity complet e dtm f transmitter/receive r i n a singl e chip standar d 6500/680 0 serie s microprocesso r port centra l offic e qualit y an d performance adjustabl e guar d time automati c ton e burs t mode cal l progres s mode singl e + 5 vol t powe r supply 20-pi n di p an d soi c packages 2 mh z microprocesso r por t operation inexpensiv e 3.5 8 mh z crystal n o continuou s f 2 cloc k required , onl y strobe application s include : pagin g systems , repeate r sys - tems/mobil e radio , interconnec t dialers , pb x systems, compute r systems , fa x machines , pa y telephones, credi t car d verification th e m-888 0 i s a complet e dtm f transmitter/receive r tha t fea- ture s adjustabl e guar d time , automati c ton e burs t mode , call progres s mode , an d a full y compatibl e 6500/680 0 microproces- so r interface . th e receive r portio n i s base d o n th e industr y stan- dar d m-887 0 dtm f receiver , whil e th e transmitte r use s a switched-capacito r digital-to-analo g converte r for low-distortion , highl y accurat e dtm f signaling . ton e burst s can b e transmitte d wit h precis e timin g b y makin g us e o f th e auto- mati c ton e burs t mode . t o analyz e cal l progres s tones , a call progres s filte r ca n b e selecte d b y a n externa l microprocessor. functional description m-888 0 function s consis t o f a high-performanc e dtm f receiver wit h a n interna l gai n settin g amplifie r an d a dtm f generato r that contain s a ton e burs t counte r fo r generatin g precis e ton e bursts an d pauses . th e cal l progres s mode , whe n selected , allow s the detectio n o f cal l progres s tones . a standar d 6500/680 0 series microprocesso r interfac e allow s acces s t o a n interna l status register , tw o contro l registers , an d tw o dat a registers. input configuration th e inpu t arrangemen t consist s o f a differentia l inpu t opera- tiona l amplifie r an d bia s source s (v ref ) fo r biasin g th e amplifier input s a t v dd /2 . provision s ar e mad e fo r th e connectio n o f a feedbac k resisto r t o th e op-am p outpu t (gs ) fo r gai n adjust - pag e 1 40-406-00012, rev. g www.clare.com figure 2 block diagram figure 1 pin diagram
ment . i n a single-ende d configuration , th e inpu t pin s shoul d be connecte d a s show n i n figur e 3 . figur e 4 show s th e necessary connection s fo r a differentia l inpu t configuration. receiver section th e lo w an d hig h grou p tone s ar e separate d b y applyin g the dtm f signa l t o th e input s o f tw o sixth-orde r switche d capacitor bandpas s filter s wit h bandwidth s tha t correspon d t o th e lo w and hig h grou p frequencie s liste d i n tabl e 2 . th e lo w grou p filte r in - corporate s notche s a t 35 0 an d 44 0 hz , providin g excellen t dial ton e rejection . eac h filte r outpu t i s followe d b y a single-order switche d capacito r filte r tha t smooth s th e signal s prio r t o limiting. limitin g i s performe d b y high-gai n comparator s wit h hysteresis t o preven t detectio n o f unwante d low-leve l signals . th e com- parato r output s provid e full-rai l logi c swing s a t th e incoming dtm f signa l frequencies. a decode r employ s digita l countin g technique s t o determin e the frequencie s o f th e incomin g tones , an d t o verif y tha t the y corre - spon d t o standar d dtm f frequencies . a comple x averagin g al - gorith m protect s agains t ton e simulatio n b y extraneou s signals (suc h a s voice) , whil e toleratin g smal l deviation s i n frequency. th e algorith m provide s a n optimu m combinatio n o f immunit y to talkof f wit h toleranc e t o interferin g frequencie s (thir d tones ) and noise . whe n th e detecto r recognize s th e presenc e o f tw o valid tone s (referre d t o a s signa l condition) , th e earl y steerin g (est) outpu t goe s t o a n activ e state . an y subsequen t los s o f signal conditio n wil l caus e es t t o assum e a n inactiv e state. steerin g circuit : befor e a decode d ton e pai r i s registered , the receive r check s fo r a vali d signa l duratio n (referre d t o a s char- acte r recognitio n condition) . thi s chec k i s performe d b y a n ex- terna l r c tim e constan t drive n b y est . a logi c hig h o n est pag e 2 M-8880 40-406-00012, rev. g www.clare.com figure 3 single-ended input configuration figure 4 differential input configuration name description in+ noninvertin g op-amp input. in- inverting op-amp input. gs gain select. gives access to output of front end differential amplifier for connection of feedback resistor. v ref reference voltage output. nominall y v dd /2 is used to bias inputs at mid-rail. v ss negative power supply input. osc1 dtmf clock/oscillator input. osc2 clock output. a 3.5795 mhz crystal connected between osc1 and osc2 completes the internal oscillator circuit. tone dual tone multifrequency (dtmf) output. r/w read/write input. controls the direction of data transfer to and from the microprocessor and the receiver/transmitter . ttl compatible. cs chip select . tt l input (cs = 0 to select the chip). rs0 register select input. see table 6 . tt l compatible. f 2 system clock input. may be continuous o r strobe d only during read or write . tt l compatible. irq /cp interrupt request to microprocessor (open-drain output). also, when call progress (cp) mode has been selected and inter - rupt enabled, th e irq /cp pin will output a rectangular wave signal representative of the input signal applied at the input op-amp. the input signal must be within the bandwidth limits of the call progress filter. see figure 11 d0 - d3 microprocessor data bus . tt l compatible. est early steering output. presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). any momentary loss of signal condition will caus e es t to return to a logic low. st/gt steering input/guard time output (bidirectional). a voltage greater tha n v tst detected at st causes the device to register the detected tone pair and update the output latch. a voltage less tha n v tst frees the device to accept a new tone pair. the g t output acts to reset the external steering time-constant; its state is a funcito n o f es t and the voltage on st. v dd positive power supply input. table 1 pin functions
cause s v c (se e figur e 5 ) t o ris e a s th e capacito r discharges. provide d tha t th e signa l conditio n i s maintaine d (es t remains high ) fo r th e validatio n perio d (t gtp ) , v c reache s th e threshold (v tst ) o f th e steerin g logi c t o registe r th e ton e pair , latchin g its correspondin g 4-bi t cod e (se e tabl e 2 ) int o th e receiv e dat a reg - ister. a t thi s poin t th e stg t outpu t i s activate d an d drive s v c t o v dd . stg t continue s t o driv e hig h a s lon g a s es t remain s high. finally , afte r a shor t dela y t o allo w th e outpu t latc h t o settle , the delaye d steerin g outpu t fla g goe s high , signalin g tha t a received ton e pai r ha s bee n registered . i t i s possibl e t o monito r th e status o f th e delaye d steerin g fla g b y checkin g th e appropriat e bi t i n the statu s register . i f interrup t mod e ha s bee n selected , th e irq /cp pi n wil l pul l lo w whe n th e delaye d steerin g fla g i s active. th e content s o f th e outpu t latc h ar e update d o n a n activ e de - laye d steerin g transition . thi s dat a i s presente d t o th e 4-bit bidirectiona l dat a bu s whe n th e receiv e dat a registe r i s read. th e steerin g circui t work s i n revers e t o validat e th e interdigit paus e betwee n signals . thus , a s wel l a s rejectin g signal s too shor t t o b e considere d valid , th e receive r wil l tolerat e signa l in - terruption s (dropout ) to o shor t t o b e considere d a vali d pause. thi s capability , togethe r wit h th e abilit y t o selec t th e steering tim e constant s externally , allow s th e designe r t o tailo r perfor - manc e t o mee t a wid e variet y o f syste m requirements. guar d tim e adjustment : th e simpl e steerin g circui t show n in figur e 5 i s adequat e fo r mos t applications . componen t values ar e chose n accordin g t o th e formula: t rec =t dp +t gtp t id =t da +t gta th e valu e o f t dp i s a devic e paramete r an d t rec i s th e minimum signa l duratio n t o b e recognize d b y th e receiver . a valu e fo r c1 o f 0. 1 m f i s recommende d fo r mos t applications , leavin g r 1 to b e selecte d b y th e designer . differen t steerin g arrangements ma y b e use d t o selec t independentl y th e guar d time s fo r tone presen t (t gtp ) an d ton e absen t (t gta ) . thi s ma y b e necessar y to mee t syste m specification s tha t plac e bot h accep t an d reject limit s o n bot h ton e duratio n an d interdigi t pause . guar d tim e ad - justmen t als o allow s th e designe r t o tailo r syste m parameters suc h a s talkof f an d nois e immunity . increasin g t rec improves talkof f performanc e sinc e i t reduce s th e probabilit y tha t tones simulate d b y speec h wil l maintai n signa l conditio n lon g enough t o b e registered . alternatively , a relativel y shor t t rec wit ha long t do woul d b e appropriat e fo r extremel y nois y environments wher e fas t acquisitio n tim e an d immunit y t o ton e dropout s are required . desig n informatio n fo r guar d tim e adjustmen t i s shown i n figur e 6. call progress filter a cal l progres s (cp ) mod e ca n b e selected , allowin g th e detec - tio n o f variou s tone s tha t identif y th e progres s o f a telephon e call o n th e network . th e cal l progres s ton e inpu t an d dtm f inpu t are common ; however , cal l progres s tone s ca n onl y b e detected whe n th e c p mod e ha s bee n selected . dtm f signal s canno t be pag e 3 M-8880 40-406-00012, rev. g www.clare.com f low f high digit d3 d2 d1 d0 697 1209 10001 697 1336 20010 697 1477 30011 770 1209 40100 770 1336 50101 770 1477 60110 852 1209 70111 852 1336 81000 852 1477 91001 941 1336 01010 941 1209 * 1011 941 1477 #1100 697 1633 a 1101 770 1633 b 1110 852 1633 c 1111 941 1633 d 0000 0 = logic low, 1 = logic high table 2 tone encoding/decoding figure 5 basic steering circuit figure 6 guard time adjustment
detecte d i f th e c p mod e ha s bee n selecte d (se e tabl e 3) . fig - ur e 7 indicate s th e usefu l detec t bandwidt h o f th e cal l progress filter . frequencie s presente d t o th e inpu t (in + an d in- ) tha t are withi n th e accept bandwidt h limit s o f th e filte r ar e hard-limited b y a high-gai n comparato r wit h th e irq /c p pi n servin g a s the output . th e squar e wav e outpu t obtaine d fro m th e schmit t trig - ge r ca n b e analyze d b y a microprocesso r o r counte r arrange - men t t o determin e th e natur e o f th e cal l progres s ton e being detected . frequencie s i n th e reject are a wil l no t b e detected, an d consequentl y ther e wil l b e n o activit y o n irq /c p a s a result o f thes e frequencies. dtmf generator th e dtm f transmitte r use d i n th e m-888 0 i s capabl e o f generat- in g al l 1 6 standar d dtm f ton e pair s wit h lo w distortio n an d high accuracy . al l frequencie s ar e derive d fro m a n externa l 3.58 mh z crystal . th e sinusoida l waveform s fo r th e individua l tones ar e digitall y synthesize d usin g ro w an d colum n programmable divider s an d switche d capacito r digital-to-analo g converters. th e ro w an d colum n tone s ar e mixe d an d filtered , providin g a dtm f signa l wit h lo w tota l harmoni c distortio n an d hig h accu - racy . t o specif y a dtm f signal , dat a conformin g t o th e encod - in g forma t show n i n tabl e 2 mus t b e writte n t o th e transmi t data register . not e tha t thi s i s th e sam e a s th e receive r outpu t code. th e individua l tone s tha t ar e generate d (f low an d f high ) ar e re - ferre d t o a s low-grou p an d high-grou p tones . typically , the high-grou p t o low-grou p amplitud e rati o (twist ) i s 2 d b t o com - pensat e fo r high-grou p attenuatio n o n lon g loops. operation : durin g writ e operation s t o th e transmi t dat a register, 4-bi t dat a o n th e bu s i s latche d an d converte d t oa2 o f8 cod e for us e b y th e programmabl e divide r circuitr y t o specif y a tim e seg - men t lengt h tha t wil l ultimatel y determin e th e ton e frequency. th e numbe r o f tim e segment s i s fixe d a t 32 , bu t th e frequenc y is varie d b y varyin g th e segmen t length . whe n th e divide r reaches th e appropriat e coun t a s determine d b y th e inpu t code , a reset puls e i s issue d an d th e counte r start s again . th e divide r output clock s anothe r counte r tha t addresse s th e sinewav e lookup rom . th e looku p tabl e contain s code s use d b y th e switched capacito r d/ a converte r t o obtai n discret e an d highl y accurate d c voltag e levels . tw o identica l circuit s ar e use d t o produce ro w an d colum n tones , whic h ar e the n mixe d usin g a low-noise summin g amplifier . th e oscillato r describe d need s n o startup tim e a s i n othe r dtm f generators , sinc e th e crysta l oscillato r is runnin g continuously , thu s providin g a hig h degre e o f ton e burst accuracy . whe n ther e i s n o ton e outpu t signal , th e ton e pin assume s a d c leve l o f 2. 5 volt s (typically) .a bandwidt h limiting filte r i s incorporate d t o attenuat e distortio n product s abov e 4 khz. burs t mode : certai n telephon y application s requir e tha t gener - ate d dtm f signal s b e o f a specifi c duration , determine d either b y th e applicatio n o r b y an y o f th e existin g exchang e transmitter specifications . standar d dtm f signa l timin g ca n b e accom - plishe d b y makin g us e o f th e burs t mode . th e transmitte r i s ca - pabl e o f issuin g symmetri c bursts/pause s o f predetermined duration . thi s burst/paus e duratio n i s 5 1 m s 1 ms , a standard interva l fo r autodiale r an d centra l offic e applications . afte r the burst/paus e ha s bee n issued , th e appropriat e bi t i s se t i n th e sta - tu s register , indicatin g tha t th e transmitte r i s read y fo r mor e data. th e timin g describe d i s availabl e whe n th e dtm f mod e has bee n selected . however , whe n cal l progres s (cp ) mod e i s se - lected , a secondar y burst/paus e tim e i s availabl e tha t extends thi s interva l t o 10 2 m s 2 ms . th e extende d interva l i s useful whe n precis e ton e burst s o f longe r tha n 5 1 m s duratio n an d 51 m s paus e ar e desired . not e tha t whe n c p mod e an d burs t mode hav e bee n selected , dtm f tone s ma y b e transmitte d onl y and not received . i n application s requirin g a nonstandard burst/paus e time , us e a softwar e timin g loo p o r externa l timer. thi s provide s th e timin g pulse s whe n th e burs t mod e i s disabled b y enablin g an d disablin g th e transmitter. th e m-888 0 i s initialize d o n poweru p sequenc e wit h dtmf mod e an d burs t mod e selected. single-ton e generation : a single-ton e mod e i s available whereb y individua l tone s fro m th e lo w grou p o r hig h grou p can b e generated . thi s mod e ca n b e use d fo r dtm f tes t equipment applications , acknowledgmen t ton e generation , an d distortion measurements . refe r t o tabl e 4 fo r details. distortio n calculations : th e m-888 0 i s capabl e o f producing precis e ton e burst s wit h minima l erro r i n frequenc y (se e table 3) . th e interna l summin g amplifie r i s followe d b y a first-order low-pas s switche d capacito r filte r t o minimiz e harmoni c compo - nent s an d intermodulatio n products . th e tota l harmoni c distor - tio n fo r a single tone can be calculated using equation 1, (see figur e 9 ) whic h i s th e rati o o f th e tota l powe r o f al l th e extrane - ou s frequencie s t o th e powe r o f th e fundamenta l frequenc y ex - presse d a s a percentage . th e fourie r component s o f th e tone outpu t correspon d t o v2f.. . vn f a s measure d o n th e output waveform . th e tota l harmoni c distortio n fo r a dual tone can be calculate d usin g equatio n 2 (se e figur e 9). pag e 4 M-8880 40-406-00012, rev. g www.clare.com figure 7 call progress response active cell output frequency (hz) specified actual % error l1 697 699.1 + 0.30 l2 770 766.2 - 0.49 l3 852 847.4 - 0.54 l4 941 948.0 + 0.74 h1 1209 1215.9 + 0.57 h2 1336 1331.7 - 0.32 h3 1447 1471.9 - 0.35 h4 1633 1645.0 + 0.73 table 3 actual frequencies vs. standard requirements
v l an d v h correspon d t o th e low-grou p an d high-grou p ampli - tude , respectively , an d v 2 imd i s th e su m o f al l th e intermodulation components . th e interna l switche d capacito r filte r followin g the d/ a converte r keep s distortio n product s dow n t o a ver y low level. dtmf clock circuit th e interna l cloc k circui t i s complete d wit h th e additio n o f a stan - dar d 3.57954 5 mh z televisio n colo r burs t crystal . a numbe r of m-888 0 device s ca n b e connecte d a s show n i n figur e 8 using onl y on e crystal. microprocessor interface th e m-888 0 use s a microprocesso r interfac e tha t allow s pre - cis e contro l o f transmitte r an d receive r functions . fiv e internal register s ar e associate d wit h th e microprocesso r interface, whic h ca n b e subdivide d int o thre e categories : dat a transfer, transceive r control , an d transceive r status . tw o register s are associate d wit h dat a transfe r operations . th e receiv e data, read-only , contain s th e outpu t cod e o f th e las t vali d dtm f tone pai r t o b e decoded . th e dat a entere d i n th e transmi t dat a regis - te r determine s whic h ton e pai r i s t o b e generate d (se e tabl e 2). dat a ca n onl y b e writte n t o th e transmi t dat a register . trans - ceive r contro l i s accomplishe d wit h tw o contro l register s (cra an d crb) , occupyin g th e sam e addres s space . a writ e opera - tio n t o cr b ca n b e execute d b y settin g th e appropriat e bi t in cra . th e followin g writ e operatio n t o th e sam e addres s will the n b e directe d t o crb , an d subsequen t writ e cycle s wil l then b e redirecte d t o cra . interna l rese t circuitr y clear s th e control pag e 5 M-8880 40-406-00012, rev. g www.clare.com bit name function description b0 tout tone output a logic 1 enables the tone output. this function can be implemented in either the burst mode or nonburs t mode. b1 cp/dtmf mode control in dtmf mode (logic 0), the device is capable of generating and receiving dtmf signals. when the call progress (cp) mode is selected (logic 1), a 6th-order bandpass filter is enabled to allow call progress tones to be detected. call progress tones within the specified bandwidth will be pre - sented at th e irq /cp pin in rectangular wave format if th e ir q bit has been enabled (b 2 =1). also, when the cp mode and burst mode have both been selected, the transmitter will issue dtmf sig - nals with a burst and pause of 102 ms (typ) duration. this signal duration is twice that obtained from the dtmf transmitter, if dtmf mode had been selected. note that dtmf signals cannot be decoded when the cp mode has been selected. b2 irq interrupt enabl e a logic 1 enables the interrupt mode. when this mode is active and the dtmf mode has been se - lected (b 1 = 0), th e irq /cp pin will pull to a logic 0 condition when either (1) a valid dtmf signal has been received and has been present for the guard time or (2) the transmitter is ready for more data (burst mode only). b3 rset register selec t a logic 1 selects control register b on the next write cycle to the control register address. subse - quent write cycles to the control register are directed back to control register a. table 4 control register a description bit name function description b0 burst burst mode a logic 0 enables the burst mode. when this mode is selected, data corresponding to the desired dtmf tone pair can be written to the transmit data register, resulting in a tone burst of a specific duration (see table 12). subsequently, a pause of the same duration is induced. immediately fol - lowing the pause, the status register is updated indicating that the transmit data register is ready for further instructions, and an interrupt will be generated if the interrupt mode has been enabled. additionally, if call progress (cp) mode has been enabled, the burst and pause duration i s increed by a factor of two. when the burst mode is not selected (logic 1), tone bursts of any desired dura- tion may be generated. b1 test test mode by enabling the test mode (logic 1), th e irq /cp pin will present the delayed steering (inverted) signal from the dtmf receiver. refer to figure 11 (b3 waveform) for details concerning the output waveform. dtmf mode must be selected (cr a b 1 = 0) before test mode can be implemented. b2 s/d single/dual tone generation a logic 0 will allow dtmf signals to be produced. if single-tone generation is enabled (logic 1), ei- ther now or column tones (low or high group) can be generated depending on the state of b3 in control register b. b3 c/r column/row tones when used in conjunction wit h b 2 (above), the transmitter can be made to generate single-row or single-column frequencies. a logic0 will select row frequencies and a logic 1 will select column fre - quencies. table 5 control register b description figure 8 common crystal connection
register s o n powerup ; however , a s a precautionar y measur e the initializatio n softwar e shoul d includ e a routin e t o clea r th e regis - ters . refe r t o table s 3 an d 4 fo r detail s o n th e contro l registers. th e irq /c p pi n ca n b e programme d t o provid e a n interrup t re - ques t signa l o n validatio n o f dtm f signals , o r whe n th e trans - mitte r i s read y fo r mor e dat a (burs t mod e only) . th e irq /c p pin i s configure d a s a n open-drai n outpu t devic e an d a s suc h re - quire s a pullu p resisto r (se e figur e 10). ordering information M-888001p 20-pin plastic dip M-8880-01sm 20-pin plasti c soic M-8880-01t 20-pin plasti c soic,tape and reel pag e 6 M-8880 40-406-00012, rev. g www.clare.com rs0 r/ w function 0 0 write to transmitter 0 1 read from receiver 1 0 write to control register 1 1 read from status register table 6 internal register functions figure 9 equations b3 b2 b1 b0 rsel irq cp/dtmf tout table 7 cr a bi t postions b3 b2 b1 b0 c/r s/d test burst table 8 cr b bit positions figure 10 application circuit (single-ended input)
pag e 7 M-8880 40-406-00012, rev. g www.clare.com parameter symbol min typ* max units operating supply voltage v dd 4.75 5.0 5.25 v operating supply current i dd 1 0 1 5 m a power consumption p o 5 0 78.75 mw inputs high-level input voltage, osc1 v iho 3.5 v low-level input voltage, osc1 v ilo 1.5 v input impedance (@ 1 khz), in+, in- r in 1 0 m w steering threshold voltage v tst 2.2 2.3 2.5 v outputs high-level output voltage (no load), osc2 v oho v dd - 0.1v v low-level output voltage (no load), osc2 v olo 0.1 v output leakage current (v oh = 2.4v) , irq i oz 1.0 10.0 m a v ref output voltage (no load) v ref 2.4 2.7 v v ref output resistance r or 1.0 k w data bus low-level input voltage v il 0.8 v high-level input voltage v ih 2.0 v low-level output voltage (i ol = 1.6 ma) v ol 0.4 v high-level output voltage (i oh = 40 0 m a) v oh 2.4 v input leakage current (v in = 0.4 to 2.4 v) i iz 10.0 m a all voltages referenced t o v ss unless otherwise noted . v dd = 5.0 v 5% ; f c = 3.57954 5 mhz ; t a = -40c to +85 c, unless otherwise noted. *typical values are for use as design aids only, and are not guaranteed or subject to production testing. table 11 dc characteristics bit name status flag set status flag cleared b0 irq interrupt has occurred. bi tone (b1) and/or bit 2 (b2) is set. interrupt is inactive. cleared after status register is read. b1 transmit data register empty (burst mode only) pause duration has terminated and transmitter is ready for new data. cleared after status register is read or when not in burst mode. b2 receive data register full valid data is in the receive data register. cleared after status register is read. b3 delayed steering set on valid detection of the absence of a dtmf sig - nal. cleared on detection of a valid dtmf signal. table 9 status register description parameter symbol value power supply voltage (v dd -v ss ) v dd + 6.0 v max voltage on any pin v dc v ss -0.3 v t o v dd + 0.3 v current on any pin i dd 10 ma max operating temperature t a -40c to +85c storage temperature t s -65c to +150c note : exceeding these ratings may cause permanent damage. functional operation under these conditions is not implied. table 10 absolute maximum ratings
M-8880 40-406-00012, rev. g www.clare.com pag e 8 parameter symbol min typ* max units receive signal conditions valid input signal levels (each tone of composite signal; notes 1, 2, 3, 5, 6, 9) -29 27.5 +1 869 dbm mv rms positive twist accept (notes 2, 3, 6, 9) 6 d b negative twist accept (notes 2, 3, 6, 9) 6 d b frequency deviation accept (notes 2, 3, 5, 9) 1.5 % 2 hz nom. frequency deviation reject (notes 2, 3, 5) 3.5% nom. third tone tolerance (notes 2, 3, 4, 5, 9, 10) -16 d b noise tolerance (notes 2, 3, 4, 5, 7, 9, 10) -12 d b dial tone tolerance (notes 2, 3, 4, 5, 8, 9, 11) +22 d b call progress lower frequency (@ -25 dbm) accept f la 320 h z upper frequency (@ -25 dbm) accept f ha 510 h z lower frequency (@ -25 dbm) reject f lr 290 h z upper frequency (@ -25 dbm) reject f hr 540 h z receive timing tone present detect time t dp 5 1 1 1 4 m s tone absent detect time t da 0.5 4 8.5 ms tone duration accept (ref. figure 12) t rec 40 ms tone duration reject (ref. figure 12) t rec 20 ms interdigi t pause accept (ref. figure 12) t id 40 ms interdigi t pause reject (ref. figure 12) t do 20 ms delay st to b3 t pstb3 1 3 m s delay st t o rx o rx 3 t pstrx 8 m s transmit timing tone burst duration (dtmf mode) t bst 50 5 2 m s tone pause duration (dtmf mode) t ps 50 5 2 m s tone burst duration (extended, call progress mode) t bste 100 104 ms tone pause duration (extended, call progress mode) t pse 100 104 ms tone output high group output level (r l = 10 k w ) v hout -6.1 -2.1 dbm low group output level (r l = 10 k w ) v lout -8.1 -4.1 dbm pre-emphasis (r l = 10 k w ) db p 0 2 3 d b output distortion (r l = 10 k w , 3.4 khz bandwidth) thd -25 d b frequency deviation (f = 3.5795 mhz) f d 0.7 1.5 % output load resistance r lt 10 5 0 k w microprocessor interface f 2 cycle period t cyc 0.5 m s f 2 high pulse width t ch 200 ns f 2 low pulse width t cl 180 n s f 2 rise and fall time t r , t f 25 ns address, r/w hold time t ah ,t rwh 10 ns address, r/w setup time (prior t o f 2) t as , t rws 23 ns table 12 ac characteristics
pag e 9 M-8880 40-406-00012, rev. g www.clare.com parameter symbol min typ* max units microprocessor interface (continued) data hold time (read) t dhr 22 ns f 2 to valid data delay (read) (200 pf load) t ddr 150 ns data setup time (write) t dsw 45 ns data hold time (write) t dhw 10 ns input capacitance, d0d3 c in 5 p f output capacitance , irq /cp c/ out 5 p f dtmf clock crystal clock frequency f c 3.5759 3.5795 3.5831 mhz clock input rise time (external clock) t lhcl 110 ns clock input fall time (external clock) t hlcl 110 ns clock input duty cycle (external clock) dc cl 40 50 60 % capacitive load, osc2 c lo 30 pf all voltages referenced to unless otherwise noted . v dd = 5.0 v 5% ; v ss = 0 v ; f c = 3.579545 mhz; t a = -40 c to +85 c *typical values are for use as design aids only, and are not guaranteed or subject to production testing. notes: 1. dbm = decibels above or below a reference power of 1 m w into a 60 0 w load. 2. digit sequence consists of all 16 dtmf tones. 3. tone duration = 40 ms. tone pause = 40 ms. 4. nominal dtmf frequencies are used. 5. both tones in the composite signal have an equal amplitude. 6. the tone pair is deviated b y 1.5 % 2 hz. 7. bandwidth limited (3 khz ) gaussia n noise. 8. the precise dial tone frequencies are 350 and 440 hz ( 2%). 9. for an error rate of less than 1 in 10,000. 10. referenced to the lowest amplitude tone in the dtmf signal. 11. referenced to the minimum valid accept level. table 12 ac characteristics (continued) parameter symbol min typ* max units input leakage current (v ss v in v dd ) i in 100 n a input resistance r in 1 0 m w input offset voltage v os 2 5 m v power supply rejection (1 khz) psrr 6 0 db common mode rejection (-3.0 v v in 3.0 v ) cmrr 6 0 db dc open-loop voltage gain a vol 6 5 d b unity gain bandwidth bw 1.5 mhz output voltage swing (r l 3 100 k w t o v ss ) v o 4.5 v pp maximum capacitive load, gs c l 100 p f maximum resistive load, gs r l 5 0 k w common mode range (no load) v cm 3.0 v pp all voltages referenced t o unless otherwise noted . v dd = 5.0 v ; v ss = 0 v; t a = 25 c *typical values are for use as design aids only, and are not guaranteed or subject to production testing. table 13 electrical characteristics - gain setting amplifier
pag e 10 M-8880 40-406-00012, rev. g www.clare.com figure 11 timing diagrams figure 12 test loads
pag e 11 M-8880 40-406-00012, rev. g www.clare.com explanation of events (a) tone bursts detected, tone duration invalid , r x data register not updated. (b) tone #n detected, tone duration valid, tone decoded and latched i n r x data register. (c) end of tone #n detected, tone absent duration valid , r x data register remain latched until next valid tone. (d) tone #n + 1 detected, tone duration valid, tone decoded and latched i n r x data register. (e) acceptable dropout of tone #n + 1, tone absent duration invalid , r x data register remain latched. (f) end of tone #n + 1 detected, tone absent duration valid , r x data register remain latched until next valid tone. explanation of symbols v in dtmf composite input signal. est early steering output. indicates detection of valid tone frequencies. st/gt steering input/guard time output. drives external rc timing circuit. rx 0 -rx 3 4-bit decoded data in receive data register. b3 delayed steering output. indicates that valid frequencies have been present/absent for the required guard time, thus constituting a valid dtmf signal. b2 output enable (input). a low level shifts q1 - q4 to its high impedance state. irq /cp interrupt is active indicating that new data is in th e r x data register. the interrupt is cleared after the status register is ready. t rec maximum dtmf signal duration not detected as valid. t rec minimum dtmf signal duration required for valid recognition. t id minimum time between valid dtmf signals. t do maximum allowable dropout during valid dtmf signal. t dp time to detect the presence of valid dtmf signals. t da time to detect the absence of valid dtmf signals. t gtp guard time, tone present. t gta guard time, tone absent. figure 13 timing diagrams
pag e 12 M-8880 40-406-00012, rev. g www.clare.com figure 14 package dimensions tolerances inches metric (mm) min max min max a .093 .104 2.35 2.65 a1 .004 .012 .10 .30 b .013 .020 .33 .51 d .496 .512 12.60 13.00 e .291 .299 7.39 7.59 e .05 0 bsc 1.2 7 bsc h .394 .419 10.00 10.65 l .016 .050 .40 1.27 tolerances inches metric (mm) min max min max a .210 5.33 a1 .015 .38 b .014 .022 .36 .56 b 2 .045 .070 1.14 1.78 c .008 .014 .20 .36 d .980 1.060 24.89 26.92 e .300 .325 7.62 8.26 e1 .240 .280 6.10 7.11 e .10 0 bsc 2.5 4 bsc e c 0 15 0 15 l .115 .150 2.92 3.81
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